Some embedded processors implement an internal Memory Protection Unit (MPU) to provide protection information for a number of variable size memory regions. Regions of memory can be write protected, as well as restricted to supervisor mode only by the MPU. These access protections are enforced on instruction fetches and data read and write accesses by comparing these access addresses with each entry in the MPU to determine a match.
Matching descriptors provide stored protection attributes which selectively allow or deny the access, and also contain memory attributes of cache-inhibited (CI) and “Guarded” (G). Due to cost concerns, the total number of region descriptors is limited, and may be overly restrictive for some memory maps.